Describe a chip. Get Verilog that is tested, measured and checked.

NVIDIA Nemotron writes every line. Locked tests decide what passes, and a formal check throws out any smaller version that differs from v1.

Built on NVIDIA Nemotron and Nebius Token Factory

Writing Verilog was never the hard part. Knowing it is right is.

14%
of ASIC and SoC projects worked on first silicon in 2024.
Wilson Research Group functional verification study, 2024 (opens in a new tab)
67,000
US semiconductor jobs projected to go unfilled by 2030, across technicians, computer scientists and engineers.
SIA and Oxford Economics, 2023 (opens in a new tab)
44.2%
of GPT-4-Turbo Verilog that passed its RTLLM v2 tests still failed a formal check.
RealBench, arXiv 2507.16200, 2025 (opens in a new tab)

Outside sources, not Verity runs.

01
You ask
Verity splits the CPU into seven blocks. Nothing runs until you press Confirm.
02
It builds and checks
Nemotron writes the blocks in parallel, and each one runs against locked tests it cannot edit. Then Nemotron writes the core that joins them.
03
Then you upgrade it
With fast memory, a 2-stage pipeline runs the benchmarks in 0.32x the time of CPU v1.

Real CPU jobs, Nebius, 2026-10-28.

Locked tests
Written from a golden model before any Verilog exists. The agent cannot edit them.
Planted bugs
We plant bugs on purpose and count how many the tests catch.
Measured
Yosys and OpenSTA measure area and clock, always against our own v1.
Proven
Yosys EQY proves a smaller version still does what v1 does.

Real CPU jobs, Nebius, 2026-10-28, against our own CPU v1. The ALU's smaller version was not proven, so the core uses its v1. Three jobs cost $1.66.

The method stays the same as chips grow: blocks, locked golden models, proofs. A new block ships only after its golden model exists.